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- SystemC/C++ Code and UML Diagram Generator
- SystemC environment setup with Docker
- Hello World
- SystemC Module
- Constructor: SC_CTOR
- SC_HAS_PROCESS
- Simulation Process
- Simulation Stages
- Time Notation
- Concurrency
- Event
- Combined Events
- Delta Cycle
- Sensitivity
- Initialization
- Process: Method
- Event Queue
- Combined Event Queue
- Mutex
- Semaphore
- FIFO
- Signal: read and write
- Signal: detect event
- Signal: many writers
- Resolved Signal
- sc_signal<bool>
- Buffer
- Communication: port
- Communication: export
- Communication: port 2 port
- Communication: specialized ports
- Communication: port array
- Primitive Channel
- Hierarchical Channel
- Trace File
- Error and Message Report
- Customized Data Type
- Clock
- Process: CTHREAD
- Handle trigger while busy
- Handle trigger while busy, template class
- Interrupt a thread while busy
- Interrupt a thread while busy, template class
SystemC
- is a C++ class library.
- provides a mechanism for managing complex systems involving large numbers of components. It is capable of modeling hardware and software together at multiple levels of abstraction. This capability is not available in traditional hardware description languages.
- allows a designer to simulate concurrent processes, each described using plain C++ syntax. SystemC processes can communicate in a simulated real-time environment, using signals of all the datatypes offered by C++, some additional ones offered by the SystemC library, as well as user defined.
- is a system-level modeling language, which mimics the hardware description languages VHDL and Verilog.
- is applied to system-level modeling, architectural exploration, performance modeling, software development, functional verification, and high-level synthesis.
- is often associated with electronic system-level (ESL) design, and with transaction-level modeling (TLM).
- is standardized in IEEE 1666-2011.
General Terminology
Below lists the most common terms used for SystemC.
| Method | A C++ method, i.e. a member function of a class. |
| Module | A structural entity, which can contain processes, ports, channels, and other modules. Modules allow expressing structural hierarchy. Module is the principle structural building block of SystemC, used to repsent a component in real systems. |
| Process | A special kind of member function of a sc_module class, registered to the SystemC simulation kernel and called only by the simulation Kernel. |
| Interface | An interface provides a set of method declarations, but provides no method implementations and no data fields. |
| Channel | A channel implements one or more interfaces, and serves as a container for communication functionality. |
| Port | A port is an object through which a module can access a channel’s interface. But modules can also access a channel’s interface directly. |
| Event | A process can suspend on, or be sensitive to, one or more events. Events allow for resuming and activating processes. |
| Sensitivity | The sensitivity of a process defines when this process will be resumed or activated. A process can be sensitive to a set of events. Whenever one of the corresponding events is triggered, the process is resumed or activated. |
SystemC Components
Below shows an example of a typical SystemC simulation with different types of components. Typically:
- processes within the same module communicate to each other via events or channels.
- processes within different modules communicate to each other via ports and channels
In this example:
- Module A is a top level module (component). It has two sub-modules (module b and module c), a channel (c1), and a simulation process (P). Module A also has one input port (p0) and two output ports (p4, p7).
- Module A receives input via port p0, and writes output via ports p4 and p7
- Module b has two simulation processes (X and Y), an event (e), an input port (p1), and two output ports (p2, p3)
- Within module b, processes X and Y are connected through event e.
- Module b connected to module A via ports p0 and p1.
- Module b also connects to process P of module A via port p3.
- Module c has two simulation processes (M and N), an input port (p5), and an output port (p6)
- Within module c, processes M and N are connected through channel c.
- Module b is connected to module c via channel c1 (ports p2 and p5 bound to c1).
- Module c connected to module A via ports p6 and p7.
- Overall, there are following signal chaines:
- ext -> p0 -> p1 -> X -> e -> Y -> p2 -> c1 -> p5 -> N - c2 - M -> p6 -> p7 -> ext
- ext -> p0 -> p1 -> X -> p3 -> P -> p4 -> ext
SystemC Execution Stages
The execution of a SystemC application consists of elaboration followed by simulation. Refer to simulation stages for details. A diagram is provided below.
As shown,
- sc_main() is the entrying point of an SystemC application. Before and after sc_start() is normal C++ code.
- Upon reaching sc_start(), SystemC simulation kernel takes over the scheduling of processes. It returns until a specified simulation time has elapsed, no more actions pending, or sc_stop() is called by any of the process.